Altera has launched 40Gbit/s Ethernet (40GbE) and 100Gbit/s Ethernet (100GbE) core intellectual property (IP) core products. These cores enable efficient construction of systems that require large amounts of standard Ethernet connectivity, including wafer-to-optical modules, wafer-to-wafer and backplane applications.
Altera Media Access Control (MAC) and Entity Encoding Sublayer and Physical Media Attachment (PCS+PMA) sublayer IP cores meet IEEE 802.3ba-2010 compliance requirements, reducing user field programmable on Altera's 28nm (nm) StraTIx V Design complexity for integrating 40GbE and 100GbE connections in logic gate arrays (FPGAs) and 40nm StraTIx IV FPGAs.
Vince Hu, vice president of enterprise and product marketing at Altera, said that more and more systems are designed to use high-speed Ethernet paths, not only the subnets of the regional network, but also the interconnections within the system. As a result, subsystem IP, including the 40GbE/100GbE MAC and PCS+PMA layers, is a key component of the system design team's tool suite.
These cores from Altera are optimized for Altera development kits and Altera Quartus II software version 12.0 integration for high performance, low cost subsystem IP in StraTIx IV and StraTIx V FPGAs. Through this development approach, Altera supports 40GbE/100GbE system-level throughput, increasing the design abstraction level of FPGA designers while improving the performance of the design team.
The interface provided by the 40GbE and 100GbE MAC and PHY IP cores, including a channel with a data suite, is logically compatible with previous generation Ethernet systems. These cores are supported by Altera Stratix V GT and GX FPGAs with transceiver speeds of up to 28.05 Gbit/s and 14.1 Gbit/s, and Stratix IV GT FPGAs with data rates up to 11.3 Gbit/s. Stratix FPGAs combine high density, high performance and rich features to enable users to integrate more features and increase system bandwidth.
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