This system is based on the use of Internet to realize remote collection of nuclear environmental information. In terms of implementation, an embedded solution based on SOPC technology is adopted. By embedding the NioslI soft core processor and the required peripheral IP Core (silicon intellectual property core) in the FPGA, and then equip the corresponding network interface to realize the utilization The Internet carries out the transmission of information.
In addition, through the development of the IP core used to control the information acquisition subsystem, and the inherent hardware parallel characteristics of FPGA, the system achieves true parallel monitoring of multiple information sources, that is, it can also perform α-ray detection while at the same time. Acquire information such as gamma rays and temperature and humidity.
1 System hardware design and implementationIn the design of this system, in order to achieve versatility, the hardware is divided into two parts in structure, namely, a general network platform for on-site monitoring and remote data transmission, and a general network platform for completing temperature and humidity, liquid level, α and γ Environmental information collection subsystem for total radiation measurement and Other tasks. The structure is shown in Figure 1 and Figure 2 respectively. The two subsystems are connected by a 40-core flat cable. In software, considering the complexity of remote data transmission using the Internet, using embedded operating system and TCP/IP protocol stack is an inevitable choice, so the hardware is also designed around this key point.
NiosII soft-core CPU is a general-purpose 32-bit RISC embedded processor launched by A137ERA. It is specially optimized for programmable logic and is equipped with a fully functional development kit, including C/C++ compiler and integrated development environment. (IDE), JTAG debugger, etc., are the core of ALTERA's programmable single-chip system solution.
As a soft core processor, NiosII provides configurable hardware and software debugging features, including basic JTAG operation control (run, stop, single step, memory, etc.), hardware breakpoints, data triggers, on-chip and off-chip Tracking, embedded logic analyzer. These powerful tools can be used in the development stage, and can be removed after debugging, saving resources. The NiosII processor also provides three different performance cores: high, medium, and low. By combining with more than 60 IP cores (UART, clock, DMA, SDRAM, parallel I/0, etc.) provided by ALTERA, designers can easily Create a perfect solution in terms of processors, peripherals, memory and I/O interfaces for specific applications. In addition, NiosII has many other excellent features, such as instruction customization, hardware accelerator, etc.
1.2 Network interface unitThe Ethernet interface chip adopts the LAN91C111 fast Ethernet controller specially used for embedded products by SMSC. The chip integrates Ethernet media access controller (MAC) and physical layer transceiver (PHY) at the same time, supports 10/100M full-duplex transmission mode, auto-negotiation and flow control functions. The host interface has multiple working modes such as synchronous bus and asynchronous bus, and can be easily connected with CPUs of various systems. In this design, the asynchronous bus interface mode is used, and the address line and data line are shared with FLASH, and it is connected to the Avalon on-chip bus through the adapter module on the FPGA.
1.3 Memory unitDue to the need to store operating system kernel, application code, program data, etc., this system uses a FLASH chip with model AM29LV320D. The chip was launched by AMD, with a capacity of 4MB and supports the CFI interface. Its connection with the AvMon bus requires a bus adapter module inside the FPGA for timing matching. SDRAM is used to store program codes and data during runtime. HY57V563220B(L)T is a 16MB SDRAM introduced by Hyundai. Since the chip port width can reach 32 bits, a single chip can be used in the system. SDRAM read and write timing is more complicated, and it is necessary to integrate a dedicated SDRAM controller IP core in the FPGA to interface with it.
2 Total count IP coreAs shown in Figure 2, the signal obtained by the α or γ detector is amplified by a linear pulse amplifier composed of two-stage amplifiers and sent to a discrimination circuit with LM393 as the core for comparison, noise is filtered out, and a rectangular pulse signal is output. For the processing of this signal, the traditional nuclear detector with MCU (microcontroller) as the core can only be realized through the combination of hardware resources (such as timers) already on the MCU and software.
This method is restricted by hardware resources and the speed of the MCU, and it is difficult to perform parallel processing on multi-channel signal sources. In this system, the total count IP core is specifically designed hardware for this problem. It is designed and implemented in VHDL language. Its internal interface conforms to the Avalon on-chip bus slave device interface specification and can be easily connected to the Avalon bus. A dedicated peripheral of NiosII soft core cPu.
The total count IP core is a part of the network platform FPGA neutron board interface, and its structure is shown in Figure 3. The principle of total alpha radiation measurement is similar to that of gamma total radiation. The following takes alpha measurement as an example to introduce its working principle. The clock source module generates an O by dividing the frequency of the main clock. The 1-second pulse signal is used as the reference source for timer timing. The timer generates the required timing information according to the acquisition time passed by the command register.
According to the timer's timing information and the command of the command register, the counter is controlled to count the pulse signals transmitted by the α measurement module, so as to obtain the count value of the total radiation amount, which is stored in the FIFO; and on the other side, NiosIICPU writes the corresponding command word to the command register of the IP core through the Avalon bus to realize the control of each channel, such as starting the total count, closing the total count, setting the acquisition time and clearing the FIFO.
It is worth noting that the α or γ count pulse from the discrimination circuit is a signal asynchronous with the working clock of the IP core, and the value of the counter ultimately needs to be stored. FIF0, therefore, the α or γ count pulses are latched and shaped twice with the main clock, so that each asynchronous count pulse generates a synchronous pulse lasting only one main clock cycle. Counting with this pulse not only solves the problem of asynchronous signal synchronization, but also effectively filters out interference pulses to make the count value accurate.
3 The software structure of the systemIn order to realize the use of Internet for remote data transmission, this system transplants the MicroC/OS2 real-time operating system and LWIP (lightweight IP protocol stack) on NiosII and then develops information acquisition software on it.
3.1 The transplantation of MicroC/OS2 and LWIPThis part of the work is mainly to transplant the specific hardware of the system and write various drivers such as temperature and humidity sensor SHT75, total counting IP core, etc. Therefore, a deep understanding of the structure and details of each layer of the software is the key to successful transplantation.
HAL is the hardware abstraction layer, which is part of the NiosII development kit, provided by ALTERA. It encapsulates the details of the hardware operation in the system, and the driver is also a part of it. HAL abstracts a total of six device models, including character mode devices, timer devices, file subsystems, Ethernet devices, DMA devices and Flash devices, and provides a series of unified initialization functions and access function interfaces for each type of device. In this way, HAL provides a POSIX-like API interface to the upper layer, that is, the hardware abstraction layer application programming interface.
The software development for NiosII is actually based on the HAL, rather than directly facing the NiosII hardware itself. Each interface IP core corresponding to the measurement module of this system is a character mode device, so the driver needs to be written according to the character mode device model in HAL.
MicroC/OS2 is a deprived real-time operating system suitable for small, microcontrollers. It supports 56 user tasks, its kernel is preemptive, supports a variety of commonly used inter-process communication mechanisms such as semaphores, mailboxes, and message queues, and provides the required multitasking environment for applications through it. Because MicroC/OS2 does not have a protocol stack itself, it is necessary to transplant a TCP/IP protocol stack LWIP to provide an interface similar to a UNIX socket to the upper layer. LWIP supports the following network protocols: IP, ARP, ICMF, UDP, TCP. The protocol stack requires 20KB of code storage space and 4KB of data storage space. At the same time, a timer dedicated to its use needs to be added when building the system.
Figure 4 shows the startup process of the analyzed system software. In this flowchart, alt_sys_init() is used to initialize the devices in the system, and the initialization program provided by the device driver is called during this process. Lwip_stack_init() is used to initialize the TCP/IP protocol stack. And tcpip_init_done() is a function that is called after the protocol stack is initialized, and the task of the communication server is also created in it. One thing to note is. All tasks based on LWIP should be created using the sys_thread_new() function instead of directly using OSTaskCreate(). Finally, after all the initializations are ready, call OSStart() to start the RTOS for task scheduling.
3.2 Design of information collection programAs a task, this module runs on the MicroC/OS2 real-time operating system to complete the measurement and control of each detection subsystem based on strategies or remote commands. The acquired information is stored in the designated memory buffer, and the results are returned as required To the remote host. For temperature and humidity measurement, because the humidity output of the SHT75 sensor is non-linear, in order to obtain accurate data, the obtained data needs to be corrected according to the given formula, while the temperature output does not need to be compensated, and the digital output is converted into The actual temperature value is sufficient, see SHT75 data manual for details. For the processing of total count, this module simply packs the data and delivers it to the communication server to send it back to the remote host.
3.3 Communication serverThis task is created by the sys_thread_new() function, as a server* agreed port, waiting for the connection of the remote host, extracting the command of the remote host, and sending the obtained command to the information collection task through the message queue; at the same time, the information is collected according to the requirements The various data obtained by the task are classified and sent back to the remote host.
LWP provides a standard Berkeley socket programming interface. This interface provides three types of sockets. Streaming sockets are used here. This is a connection-oriented reliable data transmission service, that is to say, use It is the TCP protocol. Usually, the server receives a concurrent service request and needs to activate a new process to handle this client request. However, due to system resources and simplified design considerations, the server here can only accept one connection request at a time, and this simplification is in fact also Can meet the design needs.
This system uses FPGA-based system-on-chip technology and embedded system technology to realize the connection of intelligent core instruments to the Internet, and also realizes partial reconfiguration of the hardware. You can add or delete the peripheral IP cores in the FPGA as needed. Achieve changes in the function and performance of the system. At present, the system has been applied in the radioactive sample storage room, and its function and performance meet the requirements of the actual environment. Because the network platform of this system is designed as a relatively independent subsystem, it can be applied to various corresponding fields that require remote monitoring only by developing a specific detection subsystem.
Motorola Portable Radio,Portable Two Way Radio,Motorola Vhf Handheld Radio,Multi Band Portable Radio
Guangzhou Etmy Technology Co., Ltd. , https://www.gzdigitaltalkie.com