As signal processing requirements in waveform-intensive applications such as unmanned aerial vehicles (UAVs), sonar, radar, signal intelligence (SIGINT), and software-defined radio (SDR) continue to rise, multiple digital signal processor (DSP) cores Use has become an important means of implementation. Multi-core capabilities combined with an ever-rich IP core and development tools enable superior system architecture. All of these applications require multi-core DSPs to meet the needs of mission-critical industries, including more powerful features (faster processing speeds), finer resolution, and higher accuracy. In the past, processor performance improvements were achieved through process node upgrades and increased operating clock frequencies. However, developing small process nodes and increasing clock frequency are not low-power shortcuts that improve performance. This method of integrating multiple cores in a single die achieves the high performance required at lower clock frequencies and power consumption.
Multicore DSPs are designed in system-on-a-chip (SoC) and include features such as network coprocessors, security accelerators, or FFT accelerators. To meet the performance and cost requirements of military applications, multicore DSPs should:
Support for mixed execution engine (kernel), vector signal processing (VSP), and less instruction set computing (RISC);
Provide a comprehensive multi-core advantage to achieve all the features provided by the device;
Consists of a range of devices that support scaling and re-use.
Current multi-core devices use a homogeneous core, that is, all processing cores are the same; or a heterogeneous core, that is, the device consists of different types of cores. Almost all applications require mixed processing capabilities to meet industry needs. From a developer's perspective, the focus is on supporting homogeneous cores because heterogeneous system architectures can be created with homogeneous devices. Conversely, it is difficult to achieve without sacrificing performance. Figure 1 (below) is a Texas Instruments KeyStone multicore architecture as an example of a heterogeneous multicore architecture.
Figure 1: Texas Instruments KeyStone Multicore Architecture
The parallel processing capabilities supported by multicore DSPs provide important capabilities for demanding military applications. Radar requires faster FFT response times. Depending on the FFT requirements, developers can use all or part of the core in the device to meet the FFT implementation requirements. If the performance of the FFT is implemented using a partial core, other DSP cores can perform signal pre- or post-processing in the system, or other tasks. Figure 2 shows an example of a parallel FFT. Software tools that take full advantage of multi-core advantages determine the optimal kernel configuration (number of cores) for ongoing designs. This allows developers to be highly flexible to meet multiple application needs.
Figure 2: 4 DSP Parallel FFT Implementation
Multicore DSPs are currently in a rapid development phase. The latest multi-core DSPs from semiconductor companies such as Texas Instruments use a common architecture that not only helps developers reuse software, but also saves development time for device manufacturers. Multicore DSPs are becoming a major differentiator for sonar, radar, SIGINT, and SDR applications, and are enabling exciting new system development for current and future signal processing systems.
About the author
Hector Rivera is a mission-critical marketing manager for Texas Instruments' Multicore & Media Infrastructure Products Group, where he is responsible for TI's mission-critical customer development and support, as well as multi-core DSP strategy support. Rivera has 21 years of experience in the military and government industries. He studied at George Mason University and the University of Puerto Rico with a master's degree in electrical engineering and a bachelor's degree in electrical engineering.
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