According to the different characteristics of logic functions, digital circuits can be divided into two categories, one is called combinational logic circuit (referred to as combination circuit), and the other is called sequential logic circuit (referred to as sequential circuit).
1. The characteristic of the combination logic concept combination logic circuit is that the output at any time depends only on the input at that moment, regardless of the original state of the circuit, does not involve the processing of the signal transition edge, no storage circuit, and no feedback circuit. . It can usually be expressed in the form of a truth table.
2. Verilog HDL Description of Combinatorial Logic According to the circuit behavior of combinatorial logic, two common RTL-level descriptions are available. The first is that the trigger event of the always module is a list of level sensitive signals; the second is the data flow assignment statement described by the assign keyword.
(1) The sensitivity table of the always module is a circuit with level sensitive signals.
The sensitive list of the always module is all the conditional signals and input signals, but it is important to pay attention to the integrity of the sensitive list. Various RTL keyword structures such as if, case, and for can be used in the always module. Since the assignment statement has two types of blocking assignment and non-blocking assignment, it is recommended that the reader use the blocking assignment statement "=". The signal in the always module must be defined as reg, but there are no registers in the final implementation. This is due to the fact that in the description of the combinational logic circuit, the signal is defined as reg, just to satisfy the grammar requirements.
(2) The circuit described by the assign statement can describe some relatively simple combinatorial logic circuits using the conditional "?", and the signal can only be defined as a wire type. When the combinatorial logic is more complicated, it requires a lot of assign statements or multiple nested "?", which makes the code very readable, so the first combinatorial logic modeling method is recommended at this time.
3. Combination logic considerations
(1) Sensitive Signal List In combinatorial logic design, the reader must focus on the sensitive signal list. The list of sensitive signals appears in the always block. The typical behavioral level means that as long as the signal in the sensitive signal list changes level, the statements in the always module are executed once, so the designer must pass all the input signals and conditions. The judgment signals are listed in the signal list.
Incomplete signal lists can result in different simulation and synthesis results, so the integrity of sensitive signals needs to be guaranteed. If the signal is missing, the simulation process associated with the signal cannot be triggered and the correct simulation results are not obtained. If the designer is thinking that the enumeration signal is cumbersome, use the following statement: always@(*). At this point, the synthesis tool and simulation tool will automatically add all sensitive signals to the sensitive signal list automatically.
(2) Do not introduce loops in combinatorial logic Introducing loops in combinatorial logic can cause problems such as oscillation, glitch, and collisions in the circuit, thereby reducing the stability and reliability of the design, so the loop should be completely avoided.
The reason why the logic loop is called a high-risk design is as follows:
First, the latency of the loopback logic is completely dependent on the combined logic gate delay and routing delay. Once these propagation delays have changed, the overall logic of the loop will be completely ineffective.
Second, the timing analysis of the loop is an infinite loop process. The current EDA development tools actively cut the timing path in order to calculate the timing logic of the loop, introducing many uncertain factors.
1. Sequential Logic Concepts Sequential logic is another important application in Verilog HDL design. From the point of view of circuit characteristics, it is characterized that the output at any time depends not only on the input at that moment but also on the original state of the circuit. There are storage elements in the circuit (various types of flip-flops, only D flip-flops in the FPGA chip structure) for memory information, as shown in Figure 8-7. In terms of circuit behavior, regardless of how the input changes, it is only possible to change the output when the edge of the clock (rising or falling) arrives.
(1) The reg type signals in the always block describing the sequential circuit are integrated into registers, which is different from the combinational logic circuit.
(2) Non-blocking assignment "<=" is recommended for sequential logic.
(3) The list of sensitive signals of the sequential logic only needs to be added to the clock trigger edge used. All other input and conditional decision signals are not added. This is because the timing logic is controlled by the transition edge of the clock signal.
2. Competition and adventure
(1) The competition and the wool concept signal have a certain delay when connecting the logic and the logic unit inside the combination logic circuit. The size of the delay is related to the length of the connection and the number of logic cells, and is also affected by the manufacturing process, operating voltage, temperature and other conditions of the device. In addition, the high-to-low transition of the signal also requires a certain transition time. Due to the two factors, when the level value of the multi-channel signal changes, at the moment of signal change, the output of the combinatorial logic has a sequence, not simultaneously, and some incorrect spike signals often appear. These spike signals Known as "glitch", if a "glitch" appears in a combinatorial logic circuit, it means that the circuit is "adventurous."
It should be noted that the pulse width of the adventure signal is very small, often only a few nanoseconds or tens of nanoseconds, and its bandwidth is up to hundreds of megahertz or more. In board-level debugging, if the upper limit frequency of the oscilloscope is lower, the larger burr will be displayed as a smaller glitch, which is even less noticeable. This is a problem that should be noted when capturing burrs in actual development.
Adventures can be divided into static adventures and dynamic adventures according to the different forms of production. A static adventure is a single narrow pulse that occurs when the input changes, and the output should not change; a dynamic adventure refers to the risk that the output should change when the input changes. Dynamic adventures are caused by static adventures, so there are static adventures in circuits with dynamic adventures.
Static adventures are divided into functional adventures and logical adventures according to different conditions. When there are two or more input signals that change at the same time, burrs are generated at the output. This kind of adventure is called a functional adventure. If there is only one variable that produces a change, the adventure is a logical adventure. Adventures often affect the stability of logic circuits. Clearing and setting the port is very sensitive to the glitch signal. Any glitch can cause the system to go wrong. Therefore, judging whether there is an adventure in the logic circuit and how to avoid the risk is a problem that the designer must consider.
(2) Reasons for adventures Because dynamic adventures are mainly caused by static adventures, static adventures are eliminated, and dynamic adventures are naturally eliminated. Therefore, the following describes the inspection and elimination of static adventures.
Determine whether a logic circuit will generate an adventure when certain input signals change. First, determine whether the signal will change at the same time, and then judge whether there will be an adventure when the signal changes at the same time. This can be done by a Karna map of the logic function or A logical function expression is used to make a judgment.
(1 function adventure check function adventure is caused by the logic function of the circuit, as long as the input signal does not change according to the law of the cyclic code, the combinatorial logic may generate a functional adventure, and can not be eliminated by modifying the design, only by adopting the output Clock sampling is eliminated.
(2) There are two ways to check whether the circuit generates logical adventures, namely algebraic method and Karnaugh map method.
1 Algebraic method. If a combinational logic function expression F can be reduced to a form of simplification under certain conditions, a static logic adventure may occur when A changes.
2 Karnaugh map method. In the Karnaugh map of combinatorial logic, if there is a tangency of the prime circle, a logical adventure may occur. As shown in Figure 8-16, the AC and the two prime terms are tangent. When B = C =1, A changes from 1 to 0, which will create a logical adventure.
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