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Optimization level description (for reference only):
The Code Optimization column is used to set the C51 optimization level. There are nine optimization levels (written on the book), and the high optimization level contains all of the previous optimization levels. The various levels are now described as follows:
Level 0 optimization:
1. Constant folding: Whenever possible, the compiler performs calculations that convert expressions into constant numbers, including the calculation of the run address.
2. Simple access optimization: Optimize access to the internal data and bit addresses of the 8051 system.
3. Jump optimization: The compiler always delays the jump to the final destination, so the command to jump to the jump is deleted.
Level 1 optimization:
1. Dead code elimination: The useless code segment is eliminated.
2. Jump veto: According to a test backtrack, conditional jumps are carefully checked to determine if they can be simplified or deleted.
Level 2 optimization:
1. Data coverage: Data and bit segments suitable for static coverage are identified and marked. The connection locator BL51 selects segments that can be statically covered by analyzing the global data stream.
Level 3 optimization:
1. "Peephole" Optimization: Removes redundant MOV commands, including unnecessary loading of objects from memory and loading constants. In addition, if you can save storage space or program execution time, complex operations will be replaced by simple operations.
Level 4 optimization:
1. Register Variables: Automatic variables and function parameters are placed in working registers as much as possible, and data memory space is not reserved for these variables as long as it is possible.
2. Extended access optimization: Variables from the IDATA, XDATA, PDATA, and CODE fields are directly included in the operation, so most of the time there is no need to load it into the intermediate register.
3. Local common subform elimination: If there is a repeated calculation in the expression, the result of the first calculation is saved, and if it is possible, it will be used as a follow-up calculation, so the complicated calculation can be eliminated from the code.
4, CASE / SWITCH statement optimization: The CASE / SWITCH statement as a jump table or skip string optimization.
Level 5 optimization:
1, the global common sub-elimination: whenever possible, the same sub-expression within the function is only calculated once. The intermediate result is stored in a register in place of the new calculation.
2. Simple cycle optimization: It is optimized when the cycle is re-run with constant memory.
Level 6 optimization:
Loop loop: If the program code executes faster and more efficiently, the program loop will loop.
Level 7 optimization:
1. Expanded entry optimization: DPTR data pointers are used for register variables when appropriate, pointers and array access are optimized to reduce program code and increase execution speed.
Level 8 optimization:
1. Common tail merging: When there are multiple calls to the same function, some setting codes can be reused to reduce the program code length.
Level 9 optimization:
1. Common subroutine blocks: Detect repetitive instruction sequences and convert them into subroutines. The C51 will even rearrange the code to get more reuse instruction sequences.
Of course, the optimization level is not as high as possible, and should be appropriately selected according to specific requirements.
In-depth analysis of Keil C51 bus peripheral operating problemsAfter reading the "Keil C51 Continuous Reading Method for the Same Port" article in the "Experience Exchange" column of the "Microcontroller and Embedded System Application" magazine, 2005, I believe that the article does not address this issue. Performing in-depth and accurate analysis The two solutions mentioned in the article are not straightforward and simple. The author believes that this is not a problem that Keil C51 cannot handle the continuous reading and writing of a port. It is a problem that the use of Kei1 C51 is not familiar enough and the design is not detailed. Therefore, this article is specifically written.
In this article, the three problems that are different from the original text are proposed. Each method is more direct and simple than the method mentioned in the original text, and the design is more standardized.
1 Problem review and analysisIt was mentioned in the original text that in the actual work, repeated reads of the same port were encountered and the Keil C51 compilation did not reach the expected result. The original author analyzed the assembler compiled by C and found that the second read statement on the same port was not compiled. However, it is a pity that the original author did not analyze the reasons for not being compiled, but hastily adopted some less-standard methods to test out two solutions.
For this issue, it is easy to find out the manual of Keil C51: KeilC51's compiler has an optimized setting. Different optimization settings will produce different compilation results. In general, the default compiler optimization setting is set to 8-level optimization, and the actual maximum can be set to 9-level optimization:
1. Dead code elimination.
2.Data overlaying.
3.Peephole optimization.
4.Register variables.
5. Common subexpression elimination.
6.Loop rotation.
7.Extended Index Access Optimizing.
8.Reuse Common Entry Code.
9. Common Block Subroutines.
The above problems are due to Keil C51 compiler optimization. Because in the original program, the peripheral address is directly defined as follows:
Unsigned char xdata MAX197 _at_ 0x8000
Use _at_ to define the variable MAX197 to the external expansion RAM specified address 0x8000. Therefore, the Keil C51 optimization compiler takes for granted that it is useless to repeat the second reading. The result of the first reading can be used directly, so the compiler skips the second reading statement. At this point, the problem is clear.
2 SolutionFrom the above analysis, it is very easy to propose a good solution.
2.1 The simplest and most direct way
The program does not need to be modified at all. Set the Keil C51 compiler optimization option to 0 (no optimization). Select the target of the project window, then open the "Options for Target" setting dialog box, select the "C51" tab, and select "0: Costant folding" for "Level" in "Code Optimiztaion". After compiling again, everyone will find that the compilation result is:
CLR MAXHBEN
MOV DPTR, #MAX197
MOVX A, @DPTR
MOV R7,A
MOV down8,R7
SETB MAXHBEN
MOV DPTR, #MAX197
MOVX A, @DPTR
MOV R7,A
MOV up4,R7
Two read operations are compiled.
2.2 The best way
Tell Keil C51 that this address is not an ordinary extended RAM, but a connected device that has "volatile" characteristics and that every read is meaningful. You can modify the variable definition and add the "volatile" keyword to describe its characteristics:
Unsigned char volatile xdata MAX197 _at_ 0x8000;
You can also include the system header file in the program; "#include", and then modify the variable in the program, defined as a direct address:
#define MAX197 XBYTE
In this way, Keil C51's settings can still retain advanced optimizations, and in the compilation results, the same two reads are not optimized skipped.
Schedule: Optimization Levels and Optimization Levels in Keil C51
0 Constant Consolidation: The compiler pre-computes the result, replacing the expression with a constant if possible. Including running address calculations.
Optimize simple access: The compiler optimizes access to the 8051 system's internal data and bit addresses.
Jump optimization: The compiler always extends to the final destination and multi-level jump instructions are deleted.
1 Dead code deletion: The unused code segment is deleted.
Rejected Jump: Strict check conditional jumps to determine if test logic can be inverted to improve or delete.
2 Data Coverage: Data and bit segments suitable for static coverage are identified and internally identified. The BL51 linker/locator can select segments that can be covered by global data flow analysis.
3 Peephole optimization: Clear excess MOV instructions. This includes unnecessary loading from the store and constant load operations. When storage space or execution time can be saved, simple operations replace complex operations.
4 Register variables: Automatic variables and function parameters are allocated to registers, if possible. Stores reserved for these variables are omitted.
Optimize extended access: Variables for IDATA, XDATA, PDATA, and CODE are directly included in the operation. It is not necessary to use intermediate registers for most of the time.
Local common subexpression deletion: If the same calculation is repeated with one expression, the first calculation result is saved, and it is possible to use this result later. The extra calculations are deleted.
Case/Switch Optimization: The code that contains SWITCH and CASE is optimized as a jump table or a jump queue.
5 Global common subexpression elimination: The same subexpression within a function may only be evaluated once. Intermediate results are stored in registers and used in a new calculation.
Simple loop optimization: The loop program that fills the memory area with a constant is modified and optimized.
6 Loop optimization: The program optimizes the loop if the resulting program code is faster and more efficient.
7 Extended index access optimization: Use DPTR for register variables as appropriate. Perform pointer speed and code size optimizations for pointer and array access.
8 Common tail merging: When a function has multiple calls, some setup code can be reused, thus reducing program size.
9 Common Block Subroutines: Detect loop instruction sequences and convert them to subroutines. Cx51 even rearranges the code to get a larger looping sequence.
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