First set the ModelSim.ini property in the installed ModelSim directory to the archive type (remove read-only)
Then from the DOS interface to the ISE installation directory bint (if you have already set the Xilinx path in the Windows environment variable, you don't have to)
Run the command: (for ISE 6)
Compxlib -s mTI_se -f all -l all -pe:\modeltech_6.0\win32 -oe:\modeltech_6.0\xilinx_libs (for ISE 6)
-p specifies the modelsim installation directory
-o specifies the compiled library output directory
(for ISE 7)
Compxlib -s mTI_se -arch all -lib all -l all -pe:\modeltech_6.0\win32 -dir e:\modeltech_6.0\xilinx_libs (for ISE 7)
-arch : device architecture:spartan2, virtex, etc.
-lib : library: unisim, smartmodel, etc.
The new version splits the original -f into -arch and -lib, while -f refers to reading the file, but it is also compatible with the original one.
After compiling, compxlib will automatically modify modelsim.ini, reopen ModelSim, you will see the new library.
Some common useful functions in the Q52 SE Mirror: Project --> Take Snapshot, it is easy to do version control with this;
Packing: Project --> Archive, package the project folder for easy transfer and communication
When the synthesizer has such a warning, it prompts to find the gated clock.
WARNING DesignRules: 372 - Netcheck: Gated clock. Clock net _n0019 is sourced by
a combinatorial pin. This is not good design pracTIce. Use the CE pin to
Control the loading of data into the flip-flop.
Why does the synthesizer have such a warning?
The gated clock is prone to glitches, increased latency, clock skew, and reduced testability.
Q55: How to solve these problems caused by the gated clock?Combine logic to drive the CE port instead of driving the Clock port, which is better for synchronization.
Q56: I have said so many disadvantages, is there any benefit?The benefits of gated clocks are often found in ASICs rather than FPGAs. Power consumption can be reduced by gated clocking in the ASIC. However, even in ASICs, the above shortcomings still exist, so care must be taken.
Q58: How to deal with JTAG connection? Sometimes I run into the problem: after executing the IniTIalize command in iMPACT, a series of Errors occurred, and the FPGA could not be found anyway.
If the problem you are experiencing is the same as what I described, then the following method may be able to solve it for you:
1. First confirm whether the parallel port is open:
Find the Parallel Port option in the BIOS setup and normally set it to EPP+ECP (Enhanced Parallel Port) mode.
2. Reinstall the parallel port driver that comes with ISE:
The main reason for this problem is that the parallel port driver of Xilinx ISE is overwritten, or the parallel port driver is not installed when you install ISE. Therefore, the solution is to reinstall the parallel port driver. Reminder: You only need to install the parallel port driver, instead of installing the entire ISE, the whole process can be solved in less than 1 minute.
Operation in ISE
1) Point the modelsim icon, right click property
2) VLOG command line joins -cover bcest
3) VSIM command line joins -coverage
(This article is from EDACN)
All Xilinx software cannot be installed in a directory with spaces with Chinese characters, which means it cannot be installed in the Program Files directory. It is recommended that all software be installed in the root directory of a disk.
It should be noted that SysGen can be installed in the toolbox directory of Matlab, so Matlab can not be installed in the directory with spaces with Chinese!
18K is a consideration for storing check digits. Usually, when verifying, one check digit is required for every 8 bits, so the length is 16+2=18.
However, BRAM does not generate check digits. All of its internal bit functions are consistent and can be used for storage.
When using BRAM, the storage depth is delimited by 2k. If the storage depth is <=2k, that is, the storage format is 9bit x 2k, then the 18MB BRAM can be used at this time; if the storage depth is >2k, ie 4bit x 4K or In the form of 2 bit x 8k, up to 16K of BRAM can be used.
There is a command in ISE called Toggle Path, which is used to change the relative path/absolute path storage mode of files in Project. The files mentioned here refer to files in non-project directories.
See Xilinx Answer Record 23415 for specific explanation.
iMPACT can be installed separately.
The ISE8.2 installation can choose Standalone Programming Tool, so that only impact will be installed. But remember to choose the Cable Driver you use.
But 8.2 has a problem: the installed impact will not start because of the lack of MSVCR7.dll
...
So, either you still bring a MSVCR7.dll or use another version :)
Array compare
Compare two wlf files.
Tools -> Waveform Compare -> Comparision Wizard
2. dataflow hierarchy
In the dataflow window, the hierarchy where a signal is located is displayed.
Dataflow window -> Tools -> Options -> Show Hierarchy
3. udo file
Save a do file that adds a wave with a top-level port signal so that you don't have to re-add the signal and restart the next time you turn it on. This method is the easiest way to debug.
Wave window -> File -> Save -> Format -> x.do
Open the do file and copy the useful content to the .udo file in the ISE project directory. You can add any signal after each simulation.
If you change the source code and need to recompile, you do not need to turn off ModelSim, just press the up button to execute a xx.fdo or xx.tdo file, because both fdo and tdo files will automatically call udo.
4. Verilog FSM state name
The state machine written by Verilog is a number when the state name is simulated. It would be much easier to debug using the state name.
Use virtual function. Too long, please refer to the method here.
5. ModelSim system settings
The setting information of ModelSim is modelsim.ini, and the other is in the path of the registry [HKEY_CURRENT_USER\Software\Model Technology Incorporated\ModelSim].
6. If you want to use two libraries compiled by yourself, it is well known that ModelSim PE/SE is to compile the Xilinx library. If you want both the ISE 8.1 library and the ISE 8.2 library, compiling directly twice will make ModelSim's lib extremely confusing.
The solution is to keep three modelsim.ini files, one for 8.1, one for 8.2, and one for original. 8.1 and 8.2 are well understood, when to use it, copy it to the Modelsim installation directory; the original is reserved for later compilation of other versions.
1. Modify your system structure design, or VERILOG code: This is the best method, the other is to add TIMING CONSTRAINTS, this I will say later. There are many specific methods, such as cutting large logic, using a large CLK (such as 10NS) to complete the large logic to cut into two small CLK (6NS) small logic, so although the delay is increased, but the frequency of the system goes up Your design can break through this BOTTLE NECK. What is big logic? What is small logic? You can watch static timing reports. You must understand this game, otherwise you will be playing FPGA, even if your design Can run, then you are also playing, not doing it.
The static timing report will prompt you that the PATH is the most delayed. This delay is the PATH that limits your frequency in your design. This delay has two things, logic delay and routing delay. If the logic delay is large, the logic is cut. Small logic, now FPGA is basically a 4-input SRAM, your logic input is treated as an address, and the logic result is placed in the SRAM after the FPGA configuration, so that when the FPGA is running, according to different logic inputs, Get the logical result output from SRAM. For example, if your logic is Fout = f(x, y, z, t), then x, y, z, t are treated as a sram address, and various results are placed in sram. 16 memory, according to different x, y, z, t to take the results on the Fout output, if your logic is more complex, such as 5 input signals (more than 4) to be completed in a clk Then, your logic a sram must not be completed, you need two sram, well, this is a big logic, you have to cut it, the so-called cutting is to make a temporary intermediate variable, such as F = X + Y + Z, you can divide Take two steps: the first CLK: TEMP = X + Y; second CLK: F = TEMP + Z.
Simple judgments can also be seen through the combined results. For example, in TENKNOLOGUY OR RTL VIEWER in SYNPLIFYPRO, see if your logic is in an SRAM. If it is not, it is a big logic. The other is the frequency BOTTLE NECK brought by the wiring delay. This will need to be assisted by the TIME CONSTRAINTS of the place and route.
2 TIME CONSTRAINTS: What is the difference between IC and FPGA? CONSTRAINTS! To do IC you not only have to write RTL CODE, but also add area CONSTRAINTS, timing CONSTRAINTS, power consumption CONSTRAINTS. Then you can understand how important CONSTRAINTS is now. The tools for CONSTRAINTS depend on the tools of the FPGA vendors, such as ISE QUANTUS. Also add CONSTRAINTS when writing RTL code, because it directly determines the structure of your netlist. If your RTL constraints are not well written, such as a state machine with ONHOT or GRAY CODE style, if you write ONEHOT style, but in CONSTRAINTS, the synthesis period is integrated into GRAY CODE style (now the synthesizer is very smart, you can combine the style code you wrote into the CONSTRAINTS other styles you set), then your netlist is different. The layout and routing tools behind are no longer working.
To add CONSTRAINTS, look at the CONSTRAINTS file format of the FPGA vendor, such as UCF (ISE), QSF (ALTERA). Not to mention specifically, I study hard, this is too much, for example, if you look at a logical input source and output destination too far, bring a lot of wiring delay, then add CONSTRAINTS to bring them as close as possible, but the distance It's not necessarily that they are close to the wiring. The FPGA may have a long line between two very close units. You also need to tell the layout and routing tools in CONSTRAINTS to make their wiring very short. It is not recommended to use manual cable. So that your future code can't be used as an IP, but you should use CONSTRAINTS, so that you can write the RTL code and CONSTRAINTS file later, you can sell it to the client as IP, otherwise you will keep yourself. Play and forget. CONSTRAINTS a lot, not specifically, the most important is the PERIOD or Fmax constraints, respectively corresponding to xilinx and altera, specific to learn, not much to say, the general application can use these two CONSTRAINTS
A WIFI Dongle is a pocket-size device that connects to your smartphone, tablet or laptop and allows you to access the internet while you`re traveling. It is portable, easy to carry, convenient to use, and very affordable.
150Mbps Wifi Dongle,4G Dongle,Oem Dongle,LTE Wifi Dongle
Shenhzhen Tongheng Weichuang Technology Co., Ltd , https://www.thwclte.com