1. Seven principles for FPGA device selection: device supply channel and development tool support, device hardware resources, device electrical interface standards, device speed grade, device stability level, device package and device price.
2. Spartan-3E and Spartan-3A are mainly used for logic design and simple digital signal processing. Virtex-4 LX and Virtex-5 LX are mainly used for high-speed logic operations. Virtex-4 SX and Virtex-5 SX are mainly used for high-speed complex. Digital signal processing, Virtex-4 FX and Virtex-5 FX are primarily used in embedded systems.
3. Hardware resources include: logical resources, I/O port resources, routing resources, DSP resources, memory resources, phase-locked loop resources, serial transceiver resources, and hard-core microprocessor resources.
4, excessive I / O port resource consumption may lead to two problems: FPGA overload, device heat is serious, seriously affecting the device's speed performance, work stability and life, the design should consider the heat dissipation of the device; local wiring Insufficient resources, the operating speed of the circuit is significantly reduced, and sometimes even the design can not be adapter parts, the design fails.
5, the memory resources of the device mainly have two purposes: for high-performance filters; to achieve small-capacity high-speed data buffer.
6, the area priority principle can save the logic resources inside the device, use the serial logic structure as much as possible, but at the expense of speed; and the speed priority principle guarantees the overall working speed of the device, that is, the parallel logic structure is used as much as possible. But at the expense of logical resources.
7. The principle of adding constraints is to first add global constraints, then add local constraints, and the local constraints are loose. The goal is to relax constraints as much as possible, increase the probability of successful routing, and reduce ISE placement and routing time. Typical global constraints include periodic constraints and offset constraints.
8. When adding global timing constraints, you need to divide different clock domains according to the clock frequency and add their own periodic constraints. Then add offset constraints to the input and output port signals to add additional constraints to the on-chip logic.
9. Two methods of additional clock cycle constraints: simple methods and recommended methods. The easy way is to attach the period constraint directly to the register clock network. The syntax is: [constrained signal] PERIOD = {period length} {HIGH | LOW} [pulse duration]; where the content in [] is optional, { The content in } is mandatory, and the "|" indicates the selection. Such as: Net "clk_100MHz" period = 10ns High 5ns. The recommended method is often used to constrain a clock network with complex derivation relationships with the syntax: TIMESPEC "TS_idenTIfier" = PERIOD "TNM_reference" {cycle length} {HIGH | LOW} [pulse duration]. For example: NET "clk_50MHz" = "syn_clk"; TIMESPECT "TS_sync_clk" = PERIOD "sync_clk" 20 HIGH 10. TIMESPEC uses the identifier to define the syntax of the derived clock: TIMESPEC "TS_identifier2" = PERIOD "timegroup_name" "TS_identifier1" [* | /] Multiple factor [+ | -] phasevalue [unit]. (For details, see FPGA Development Raiders, page 45).
10. The direct causes of poor timing performance can be divided into three categories: poor layout, excessive logic levels, and excessive signal fanout.
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