Abstract: The implementation of embedded TCP/IP communication protocol stack on Xilinx FPGA is studied. The system composition and principle of software and hardware are introduced. An efficient working mode of TCP/IP protocol stack on real-time operating system is proposed, and it is in Virtex5. The migration on the FPGA was successful. Through the establishment of test platform for data transmission test, it proves that it has stable and efficient communication performance, which provides a new idea for embedded device development.
With the development of electronic information technology, network is becoming more and more popular. Ethernet is widely used in various fields. As long as a network interface is added to the device and the TCP/IP protocol is implemented, it can be easily accessed into the existing network. Complete the functions related to remote data transmission. Therefore, embedded network technology has always been the focus of attention, and has been widely used in various fields such as communication, industrial control, and consumer electronics. In recent years, with the rapid development of programmable logic devices, people began to consider the integration of the entire embedded system into a single FPGA, including the embedded system-on-chip of Ethernet. Based on the practical application, this paper builds an embedded network hardware development platform based on the system-on-chip (SystemonChip) built by the soft core CPU MicroBlaze IPCore of Xilinx FPGA, and realizes the TCP/IP communication protocol stack LwIP (Lightweight Internet Protocol) in real-time operating system. Porting on Xilkernel. The system composition and principle of its software and hardware are introduced in detail. The on-chip system configuration of FPGA, its driver layer and protocol stack layer software structure are expounded, and some key source codes are given.
Xilinx offers a wide range of components and resources for embedded network communication solutions. One of the key benefits of Xilinx's embedded solutions is the flexibility and scalability of its processors, IP cores, and software components. Its flexibility allows users to turn on or off options for processors, IP cores, and software platforms as needed. Advanced features, and many independent parameters can be fine-tuned until the application requirements are met at the software level.
The system uses Xilinx's FPGA chip XC5VFX70T as the hardware design platform, MicroBlaze soft core as the central processor, VHDL hardware description language to implement the co-processing function module, and the on-chip bus connection MicroBlaze processor and peripheral device (IP) to build the embedded System on chip.
Xilinx uses the IBM CoreConnect bus communication chain as the on-chip bus of the embedded processor, providing a wealth of interface resources, mainly PLB (Processor Local Bus) interface, high-speed LMB (Local Memory Bus). Interface, FSL (Fast Simplex Link) master-slave interface, XCL (Xilinx Cache Link) interface. The PLB bus can connect peripheral IP cores to the MicroBlaze system, which is often used in applications where speed is not critical; LMB is dedicated to high-speed access to on-chip block RAM; and XCL is used to achieve high-speed access to off-chip memory. FSL is a FIFO-based unidirectional link unique to MicroBlaze processors. It can directly connect point-to-point with user-defined IP cores and MicroBlaze internal general-purpose registers. It is generally used in applications where transmission speed is high.
The implemented system consists of MicroBlaze processor, ILMB bus, DLMB bus, Block RAM, DDR SDRAM, 10 /100/1000 Soft TEMAC, GPIO interface, UART16550 serial port, PLB TIMER timer, and DDC based on PLB bus technology. Variable frequency) Custom IPCore and FFT (Fast Fourier Transform) custom IPCore based on FSL bus technology. The system architecture of the design is shown in Figure 1. The entire system is built in Xilinx's EDK development tool and has full programmable features to change the relevant configuration parameters according to different task requirements.
Figure 1 system architecture diagram
2 system software platform design 2.1 LwIP protocol stack
LwIP is an open source TCP/IP protocol stack. It reduces the occupation of RAM on the basis of the main functions of the TCP/IP protocol stack. Generally, it only needs tens of KB of RAM and about 40 KB of ROM to run, so it is very suitable. Used in embedded systems with low hardware configurations. EDK provides a good interface for the LwIP library and provides an adapter for the Xilinx TEMAC IP core. The LwIP protocol stack is conveniently used in the EDK project to implement network functions. LwIP has the following characteristics:
1 Support IP forwarding under multiple network interfaces;
2 Support ICMP protocol;
3 Includes experimentally extended UDP (User Datagram Protocol);
4 TCP (Transmission Control Protocol) including blocking control, RTT estimation, and fast recovery and forwarding;
5 Provide a dedicated internal callback interface (Raw API) to improve application performance;
6 optional Berkeley interface API (in the case of multi-threading);
7 Support for ppp in the latest version;
8 Added support for IP fragments in the new version;
9 Supports the DHCP protocol and dynamically assigns IP addresses.
In Xilinx's embedded development tool EDK, the version of LwIP is lwip130, which is the v1.3.0 version of LwIP. The LwIP library provides two types of API functions, RAW mode and Socket mode. The former is for high performance and the latter is for general purpose, providing a standard set of Socket API interface functions.
2.2 Xilkernel real-time operating system
Xilkernel is a small, modular embedded real-time operating system for EDK systems from Xilinx that supports MicroBlaze, PowerPC405 and PowerPC440 processors. Xilkernel is a dedicated embedded operating system with complete kernel, low CPU resources, fast running speed, minimum response time interval of 1 ms, and tight integration with EDK-generated hardware system. Supporting Portable Operating System Interface (POSIX), it is an ideal operating system for small and medium-sized designs. Its internal structure is shown in Figure 2.
Figure 2 Schematic diagram of Xilkernel internal structure
Xilkernel itself does not have a file processing system and TCP/IP protocol stack, but has a good interface with the LwIP library and supports the LibXil MFS file system library, so it can also form a more complex embedded system. It has the following characteristics:
1 Kernel configuration features have been integrated into the EDK tool for ease of use and convenience;
2 When the kernel starts, statically create threads and dynamically allocate memory;
3 can load or unload different functional modules to achieve the scalability of the kernel;
4 provides a set of POSIX-compliant API user program interface functions;
5 All system call functions are protected with parameter validity check and return a POSIX compliant error code.
3.1 Socket application development
The LwIP Socket API is based on the multi-threaded task of the Xilkernel operating system. It is very similar to the BSD standard Socket API. It has the characteristics of less development difficulty and user-friendly calling, which can meet the requirements of general network applications. To use the LwIP socket mode, first call the lwip_init() function in the initialization thread to initialize the LwIP protocol stack, and then use the sys_thread_new() function to generate a new thread, that is, enter the main thread. In the main thread, first add the network interface through the xemac_add() function, then open a thread for the xemacif_input_thread() function, and transplant the data packet received from the interrupt response process to the thread running the Lemap xemacif_input_thread() function. The thread notifies when the LwIP packet arrives and buffers the data by receiving the interrupt handler. The following is the network interface program code added to the main thread:
......
Struct ip_addr ipaddr, netmask, gw;
Struct neTIf *neTIf;
neTIf = &server_netif;
/* Initialize IP address*/
IP4_ADDR(&gw, 000,000,000,000); //Set the gateway
IP4_ADDR(&ipaddr, 192,168,169,110);//Set IP
IP4_ADDR(&netmask,255,255,255,000); //Set subnet IP
/*Join the network interface and set it as the default interface*/
If(!xemac_add(netif,&ipaddr,&netmask,&gw,fullmac,XPAR_LLTEMAC_0_BASEADDR)){
Xil_printf("Error adding N/W interface\\");
Return;
}
Netif_set_default(netif);
/*Enable network interface*/
Netif_set_up(netif);
/*Enable packet receiving thread*/
Sys_thread_new("xemacif_input_thread",xemacif_input_thread,netif,THREAD_STACKSIZE,MY_THREAD_PRIO);
/*Create Socket interface*/
Sock = socket(AF_INET, SOCK_STREAM, 0);
Addr.sin_family = AF_INET;
Addr.sin_port = htons(6000);
Addr.sin_addr.s_addr = INADDR_ANY;
Bind(sock,(struct sockaddr *)&addr,sizeof(addr));
Listen(sock,15);
While(1){
s = accept(sock,(struct sockaddr*)&rem,&len);
......
}
After the above steps, the network server can be established using Socket programming.
3.2 Network Data Transmission Performance Test The Xilinx XC5VFX70T development board is directly connected to the PC using an RJ45 crossover Ethernet cable. The PC is used as the client of TCP/IP. The Xilinx XC5VFX70T development board serves as the server of TCP/IP. After the client responds via the connection, it continuously sends TCP packets to the server. After receiving the data, the server calculates the total amount of data received, and does not perform other processing. Use iperf network test software to test the performance of the system network directly sending data.
In Socket mode, the network sending rate is 27.2 Mb/s, and the result of the iperf server is shown in Figure 3.
Figure 3 LwIP protocol stack send data rate test results
In order to detect the rate of data transmission and its accuracy in the application developed in this paper, the LabView software development network service client is used to receive the data of the system on the computer side, and the data is recorded as a DAT file, and the test is performed by using the NetPerSec network test software. The current rate and average rate of the network. At a write data rate of 24.1 Mb/s, NetPerSec shows an average network reception rate of 24.8 Mb/s; the recorded DAT file shows no jump points in the graph, and the data is not lost. NetPerSec screenshots and DAT file display graphics are shown in Figure 4. Show.
Figure 4 NetPerSec network data traffic statistics and linear data correctness test
When the write data rate is 24.3 Mb/s, NetPerSec shows that the network receiving average rate is 25.4 Mb/s; the recorded DAT data shows a jump point in the middle of the graph, indicating that there is packet loss, NetPerSec screenshot and DAT data display graph as shown in Figure 5. Shown.
Figure 5 NetPerSec network data traffic statistics and data loss test
The test results show that the network data transmission using the LwIP protocol stack Socket mode can achieve stable data transmission with a network speed of 24.8 Mb/s and a receiving reconnaissance signal bandwidth of 750 kHz.
Conclusion This paper studies the implementation of TCP/IP communication protocol on Xilinx FPGA, and introduces the system composition and principle of its hardware and software. Its functions can be customized according to needs. It not only introduces the soft core processor and embedded operating system Xilkernel, but also applies the LwIP TCP/IP protocol stack. At the same time, it uses a large number of IP cores, and the system construction is very flexible. The design of its software and hardware part adopts a separate design architecture, which makes the whole system modification and reconstruction more convenient, and realizes the embedded system on chip.
references
[1] Xilinx Inc. ML402 User Guider, 2005.
[2] Xilinx Inc. MicroBlaze Processor Reference Guide, 2008.
[3] Xilinx Inc. OS and Libraries Document Collection, 2008.
[4] Xilinx Inc. UG650: LwIP 1.3.0 Liabrary (v1.00.b), 2009.
[5] Tian Wei, Xu Wenbo, Hu Bin, et al. Xilinx ISE Design Suite 10.x FPGA Development Guide [M]. Beijing: People's Posts and Telecommunications Press, 2008.
[6] Bao Xingchuan. Implementation of TCP/IP Communication Technology on Xilinx FPGA[J]. Water Resources and Hydrology Automation, 2007, 6(2): 2022.
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