In actual work, the working state of the trigger is determined not only by the trigger input signal, but also by a certain beat. To do this, you need to add a clock control terminal.
1. Level-triggered SR flip-flop Synchronous RS trigger clock pulse CP only controls the state of the trigger to allow change, whether the state of the trigger becomes 0 or 1, or is unchanged by the input R, S .
Setting or resetting the flip-flop with SD' or RD' should be done with CLK=0, otherwise the preset state may not be saved after SD' or RD' returns high.
Level trigger mode of action features:
During the entire period of CP=1, the change of the input signal directly changes the state of the output terminals Q and Q';
When CP=1, if the input signal changes several times, the trigger state will be reversed multiple times, so its anti-interference ability is poor. If the S signal has a small interference (positive pulse), the Q flips to the 1 state and cannot be maintained. 0 state;
The phenomenon of multiple flips occurring during CP 1 is called flipping, which is a kind of danger of sequential circuits;
The output state remains unchanged during CP =0.
2. D latch characteristic equation: Q*=D
Features: Q* follows the D signal
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