The digital broadcasting AM system DRM (Digital Radio Mondiale) adopts advanced audio coding AAC (Advanced Audio Coding) as its main source coding method, and achieves FM sound quality in the same bandwidth (9 kHz or 10 kHz) as analog AM broadcasting . DRM not only solves the shortcomings of poor anti-interference ability of analog AM broadcasting, but also adds additional services such as text, image, and data on the basis of audio services, which enriches the content of AM broadcasting and greatly improves the market competitiveness of AM broadcasting. Become an inevitable trend in the development of AM broadcasting.
Source coding is the key technology of the DRM system. It compresses the program audio source signal and requires less transmission bandwidth to ensure that the reconstructed audio signal at the receiving end has better sound quality. The implementation and optimization of the DRM audio decoder determines whether the system can correctly implement audio decoding and complete real-time audio playback, so that users can get good sound quality. In this paper, the AAC audio decoding program runs on the DSP hardware platform. Due to the limited performance of the hardware platform, the audio decoder must not only ensure the audio quality, but also not occupy too many resources of the DSP system. Therefore, it is of great practical significance to study the implementation and optimization of DRM audio decoder on a high-performance DSP platform.
1. DRM audio decoding process
The principle and implementation technology of the general MPEG-4 AAC audio codec are already mature and will not be described in detail. The frequency band recovery technology (SBR) used in the source coding scheme of the DRM system provides a function similar to the perceptual noise shaping (PNS) module in MPEG-4 AAC. Therefore, the audio coding scheme adopted by the DRM system does not include the PNS module. It also removes complex modules such as long-term prediction (LTP) and scalable sampling rate (SSR), which reduces the complexity of the algorithm and requires relatively low processing power of the processor. It is suitable for use on embedded development platforms. The sampling rate of AAC is 12 kHz and 24 kHz. 5 (12 kHz sampling frequency) or 10 (24 kHz sampling frequency) audio frames form an audio super frame with a fixed duration of 400 ms. Before optimizing this article, the correct decoding and real-time playback of the DRM broadcast signal were first implemented in the VC ++ 6.0 environment of the PC. The test signal was mono, 48 kHz sampling, and the DRM broadcast signal source in the wav format using AAC audio encoding. The sampling rate of AAC is 24 kHz, that is, an audio superframe contains 10 subframes. Run the whole project in VC ++ 6.0 environment, obtain the AAC audio coded data in the DRM signal source after synchronization, demodulation and channel decoding, and output each subframe data to a file before each AAC subframe decoding. When testing the audio decoding program on the DSP, you can directly extract the AAC data for decoding.
(1) Perform bitstream decomposition on the transmitted AAC subframe data, and obtain data of various parts such as syntax units and Huffman codewords according to the audio subframe structure in the DRM system.
(2) Perform Huffman decoding. This part uses a series of Huffman codebooks for query decoding. The frequency domain data and scale factor are obtained in this step. This process requires Huffman decoding while recombining the scrambled codewords, and the decoded data is placed in the correct position, ready for the next dequantization.
(3) Inverse quantization of the decoded frequency domain data.
(4) Multiply the result of inverse quantization by the scale factor generated in (2).
(5) Part of the filter bank. This part uses inverse modified discrete cosine transform (IMDCT) in decoding, and also includes a windowing process and superposition process. The output of the function module is the time domain value of the signal.
2. TMS320C6416 DSP development platform
TMS320C6416 (C6416 for short) is a high-performance 32-bit fixed-point DSP chip. The working frequency of C6416 used in this article reaches 600 MHz. Its features include: advanced ultra-long instruction architecture CPU with 8 functional units; all instructions are executed conditionally; support 8/16/32 bit variable-length data access; support saturation and normalization operations of commonly used arithmetic operations; Two-level cache (Cache) memory structure and rich on-chip peripherals, such as enhanced direct memory access EDMA controller, multi-channel buffer serial port McBSP, etc. In addition to the C6416 DSP chip, the C6416 development board also has an externally expanded 512 K & TImes; 8 bit FLASH.
The development environment uses the DSP integrated development environment CCS (Code Composer Studio), which integrates code editing, compilation, project management, code generation and debugging, code performance analysis, data viewing, drawing data images, DSP / BIOS parameter settings, and provides various A variety of optimization and other tool modules.
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